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M74HCT7259
8 BIT ADDRESSABLE LATCH/DECODER/RELAIS DRIVER (OPEN DRAIN, INVERTING OUTPUT)
.LOWPOWERDI .COMPATI .OUTPUTDRI .HI
DESCRIPTION
SSIPATION ICC = 4 A (MAX.) AT TA = 25 C BLE WITH TTL OUTPUTS VIH = 2V (MIN) VIL = 0.8V (MAX) VE CAPABILITY 90 LSTTL LOADS GH CURRENT OPEN DRAIN OUTPUT UP TO 80 mA
B1R (Plastic Package)
The M74HCT7259 is a high speed CMOS 8 BIT ADDRESSABLE LATCH/DECODER fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. The M74HCT7259 has single data input (D) 8 LATCH inverted OUTPUTS (Q0-Q7), 3 address inputs (A, B and C), common enable input (ENABLE) and a common CLEAR input. To operate this device as an addressable latch, data is held on the D input, and the address of the latch into which the data is to be entered is held on the A, B and C inputs. When ENABLE is taken low the data flows through to the address output. The data is stored on the positive-going edge of the ENABLE pulse. All unadressed latches will remain unaffected. With ENABLE in the high state the device is deselected and all latches remain in their previous state, unaffected by changes on the data or address inputs. To eliminate the possibility of entering erroneous data into the latches, the ENABLE should be held high INPUT AND OUTPUT EQUIVALENT CIRCUIT
M1R (Micro Package)
C1R (Chip Carrier)
ORDER CODES : M74HCT7259B1R M74HCT7259M1R M74HCT7259C1R
PIN CONNECTIONS (top view)
NC = No Internal Connection
December 1992
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(inactive) while the address lines are changing. If ENABLE is held high and CLEAR is taken low all eight latches are cleared to the HIGH (OFF) state. If ENABLE is low all latches except the addressed latch will be cleared. The address latch will instead be the complement of the D input,effectively impleLOGIC DIAGRAM menting a 3 to 8 line decoder. Internal clamp diodes protect the open drain outputs against over voltages due to inductive loads. All inputs are equipped with protection circuits against static discharge and transient excess voltage.
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PIN DESCRIPTION
PIN No 1, 2, 3 4, 5, 6, 7, 9, 10, 11, 12 13 14 15 8 16 SYMBOL A, B, C Q0 to Q7 DATA IN ENABLE CLEAR GND VCC NAME AND FUNCTION Latch Select latch Outputs Data Inputs Latch Enable Input Conditional Reset Input Ground (0V) Positive Supply Voltage
IEC LOGIC SYMBOL
TRUTH TABLE
INPUTS CLEAR H H L L ENABLE L H L H OUTPUTS OF ADDRESSED LATCH D Qi0 D H SELECT INPUTS C L L L L H H H H B L L H H L L H H A L H L H L H L H EACH OTHER OUTPUT QI0 Qi0 H H FUNCTION ADDRESSABLE LATCH MEMORY 8-LINE DEMULTIPLEXER CLEAR ALL BITS TO "H"
LATCH ADDRESSED Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
D: The level at the data input Qi0: The level before the indicated steady state input conditions were established, (i = 0,1,....,7).
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ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IIK IOK IO IGND ICC PD Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Per Pin DC Ground Current DC VCC Current Power Dissipation Storage Temperature Lead Temperature 10 sec Parameter Value -0.5 to +7 -0.5 to VDD + 0.5 -0.5 to VDD + 0.5 20 20 100 - 800 50 500 (*) -65 to +150 300 Unit V V V mA mA mA mA mA mW o C
o
C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition isnotimplied. (*) 500 mW: 65 oC derate to 300 mW by 10mW/oC: 65 oC to 85 oC
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO Top tr, tf Parameter Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time Value 4.5 to 5.5 0 to VCC 0 to VCC -40 to +85 0 to 500 Unit V V
o
V C
ns
DC SPECIFICATIONS
Test Conditions Symbol VIH Parameter High Level Input Voltage VCC (V) 4.5 to 5.5 4.5 to 5.5 4.5 IOZ IIN ICC Output Leackage Current Input Leakage Current Quiescent Supply Current VI = VIH or VIL IO= 20 A IO= 36 mA IO= 80 mA 0.0 0.17 0.32 Value TA = 25 oC Min. Typ. Max. 2.0 -40 to 85 oC Min. Max. 2.0 V 0.8 0.8 V 0.1 0.26 0.40 5 0.1 4 3.0 0.1 0.33 0.50 50 1 40 3.9 A A A mA Unit
V IL
Low Level Input Voltage Low Level Output Voltage
VOL
V
5.5 5.5
VI = VIH or VIL VOUT = VCC or GND VI = VCC or GND VI = VCC or GND Each Input in Turn: VIN = 0.5 V or 2.4 V All Other Inputs: V CC or GND
5.5
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AC ELECTRICAL CHARACTERISTICS (C L = 50 pF, Input t r = tf = 6 ns)
Test Conditions Symbol tTLH tPLZ tPZL tPLZ tPZL tPLZ tPZL tPLZ tPZL tW(L) tW(L) ts th CIN CPD (*) Parameter Output Transition Time Propagation Delay Time (DATA - Q) Propagation Delay Time (A, B, C - Q) Propagation Delay Time (ENABLE - Q) Propagation Delay Time (CLEAR - Q) Minimum Pulse Width (CLEAR) Minimum Pulse Width (ENABLE) Minimum Set-Up Time Minimum Hold Time Input Capacitance Power Dissipation Capacitance VCC (V) 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 CL (pF) 50 50 150 50 150 50 150 50 150 50 50 50 50 RL (K) 1 1 1 1 1 1 1 1 1 1 1 1 1 5 96
o
Value TA = 25 C Min. Typ. Max. 3 20 24 25 29 21 25 19 23 7 7 4 6 31 37 39 45 33 39 30 36 15 15 10 5 10 -40 to 85 oC Min. Max. 9 39 46 49 56 41 49 38 45 19 19 13 5 10 Unit ns ns ns ns ns ns ns ns ns pF pF
(*) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD *VCC *fIN + ICC
SWITCHING CHARACTERISTICS TEST WAVEFORMS WAVEFORM 1: (ENABLE = L, CLR = H, A-C= STABLE)
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WAVEFORM 2: (ENABLE = L)
WAVEFORM 3: (CLR = H, A-C = STABLE)
WAVEFORM 4: (D = H, A-C = STABLE)
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WAVEFORM 5: (CLR = H)
TEST CIRCUIT ICC (Opr.)
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Plastic DIP16 (0.25) MECHANICAL DATA
mm MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP. MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 inch TYP. MAX.
DIM.
P001C
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SO16 (Narrow) MECHANICAL DATA
DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm TYP. MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.004 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010
P013H
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PLCC20 MECHANICAL DATA
mm MIN. A B D d1 d2 E e e3 F G M M1 1.27 1.14 7.37 1.27 5.08 0.38 0.101 0.050 0.045 9.78 8.89 4.2 2.54 0.56 8.38 0.290 0.050 0.200 0.015 0.004 TYP. MAX. 10.03 9.04 4.57 MIN. 0.385 0.350 0.165 0.100 0.022 0.330 inch TYP. MAX. 0.395 0.356 0.180
DIM.
P027A
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Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics. (c) 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A
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